The present invention relates generally to channel equalization and decoding techniques, and more particularly, to sequence estimation techniques with reduced complexity.
The transmission rates for local area networks (LANs) that use twisted pair conductors have progressively increased from 10 Megabits-per-second (Mbps) to 1 Gigabit-per-second (Gbps). The Gigabit Ethernet 1000 Base-T standard, for example, operates at a clock rate of 125 MHz and uses four copper pairs to transmit 1 Gbps. Trellis-coded modulation (TCM) is employed by the transmitter, in a known manner, to achieve asymptotic coding gains. The signals arriving at the receiver are typically corrupted by intersymbol interference (ISI), crosstalk, echo, and noise. A major challenge for receivers in such a channel environment is to jointly equalize the channel and decode the corrupted trellis-coded signals at such high clock rates. As the high processing speed requires a parallel implementation without resource sharing, managing hardware complexity becomes difficult. Another issue is to meet the speed requirements, as the algorithms for joint equalization and decoding incorporate non-linear feedback loops which cannot be pipelined.
Data detection is often performed using maximum likelihood sequence estimation (MLSE), to produce the output symbols or bits. A maximum likelihood sequence estimator considers all possible sequences and determines which sequence was actually transmitted, in a known manner. The maximum likelihood sequence estimator is the optimum decoder and applies the well-known Viterbi algorithm to the combined code and channel trellis. For a more detailed discussion of a Viterbi implementation of a maximum likelihood sequence estimator, see Gerhard Fettweis and Heinrich Meyr, xe2x80x9cHigh-Speed Parallel Viterbi Decoding Algorithm and VLSI-Architecture,xe2x80x9d IEEE Communication Magazine (May 1991), incorporated by reference herein.
The computation and storage requirements of the Viterbi algorithm are proportional to the number of states. The number of states of the combined trellis is given by Sxc3x972mL, where S is the number of code states, m is the number of bits for each information symbol, and L is the length of the channel memory. For the Gigabit Ethernet standard, for example, S=8, m=8, and L≈10, which leads to a prohibitively expensive Viterbi algorithm with about 1025 states.
In order to manage the hardware complexity for the maximum likelihood sequence estimator that applies the Viterbi algorithm, a number of sub-optimal approaches, such as xe2x80x9creduced state sequence estimation (RSSE)xe2x80x9d algorithms, have been proposed or suggested. For a discussion of reduced state sequence estimation techniques, see, for example, P. R. Chevillat and E. Eleftheriou, xe2x80x9cDecoding of Trellis-Encoded Signals in the Presence of Intersymbol Interference and Noisexe2x80x9d, IEEE Trans. Commun., vol. 37, 669-76, (July 1989) and M. V. Eyuboglu and S. U. H. Qureshi, xe2x80x9cReduced-State Sequence Estimation For Coded Modulation On Intersymbol Interference Channelsxe2x80x9d, IEEE JSAC, vol. 7, 989-95 (August 1989), each incorporated by reference herein.
Generally, reduced state sequence estimation techniques reduce the complexity of the maximum likelihood sequence estimators by merging multiple states of the full combined channel/code trellis. Although RSSE techniques reduce the number of states for Viterbi decoding, the required computations are still too complex at the high clock rates associated with the Gigabit Ethernet standard, as the high processing speeds require a parallel implementation without resource sharing. In addition, the RSSE technique incorporates non-linear feedback loops which cannot be pipelined. The critical path associated with these feedback loops is the limiting factor for high-speed implementations. Simplifying the RSSE technique by further reducing the number of states or by doing separate equalization with a decision-feedback equalizer (DFE) and decoding of the TCM codes comes often with a significant penalty in terms of signal-to-noise ratio (SNR) performance. As apparent from the above-described deficiencies with conventional reduced state sequence estimation algorithms, a need exists for a reduced state sequence estimation algorithm that reduces the hardware complexity of RSSE techniques for a given number of states and also relaxes the critical path problem.
Generally, a method and apparatus are disclosed for reducing the complexity of the RSSE technique for a given number of states while also relaxing the critical path problem. A communications channel is represented using a discrete time model, where the channel impulse response has a memory length, L, denoted by {fk}k=0L, where fk is the coefficient for channel tap k. The signal energy of a pulse that has gone through a minimum-phase channel is concentrated in the initial taps. As used herein, taps one through U are referred to as the initial taps, and taps U+1 through L are referred to as the tail taps, where U is a prescribed number. In one implemenatation, the tap number, U, is selected to ensure that the initial taps contribute a predefined percentage of the overall signal energy.
According to one aspect of the invention, the less significant tail taps (U+1 through L) are processed with a lower complexity cancellation algorithm, such as a decision-feedback equalizer technique, that cancels the tail taps using tentative decisions. Thereafter, only the more significant initial taps (1 through U) are processed with a reduced state sequence estimation technique. The DFE technique initially removes the intersymbol interference associated with the tail taps, then the RSSE technique is applied only to the more important tail taps. Thus, only taps one through U are processed using the RSSE technique, while taps U+1 through L are processed with a lower complexity decision-feedback equalizer. The present invention does not further reduce the number of states which are processed in the RSSE circuit, thus ensuring a good bit error rate versus signal-to-noise ratio performance for a well-chosen value of U. Meanwhile, the computational complexity and processing time of the decision-feedback computations in the RSSE circuit are substantially reduced. The hardware complexity of the survivor memory unit (SMU) in the RSSE circuit can also be reduced.
A receiver is disclosed that includes a tentativnre decision/tail processing circuit for processing the less significant tail taps and an RSSE circuit for processing the initial taps. The tentative decision/tail processing circuit processes the less significant tail taps with a lower complexity DFE algorithm, to cancel the tail taps using tentative decisions. The RSSE circuit processes only the initial taps with the RSSE technique.